1. Field of the Invention
The present invention relates to the manufacture of integrated circuit devices incorporating different thicknesses of gate oxides on the surface of a substrate.
2. Description of the Related Art
Field effect transistors (FETs) are one of the most widely used devices in integrated circuits because FET circuits can be made to perform a wide variety of functions and FET devices can be manufactured having highly reproducible and predictable properties. Another advantage of FET devices is that they can be made very small and can be packed closely together. A typical FET consists of source and drain electrodes spaced apart in a substrate on either side of a channel region and a conductive gate electrode separated from the channel region by a gate oxide layer. The FET is formed on a surface of a silicon or other semiconductor substrate having a background doping of a first conductivity type. A layer of gate oxide is provided on the surface of the substrate, generally by thermal oxidation so as to provide a uniform and dense oxide layer having a predictable thickness and a predictable and low level of fixed charge. The gate electrode is next formed by depositing and patterning a layer of polysilicon, which may be rendered conductive by doping in situ during deposition or by diffusion or ion implantation after deposition. Frequently, a layer of a conductive material such as metal or metal silicide is provided on the layer of polysilicon to reduce the resistivity of the gate electrode. The source and drain electrodes are formed in the substrate by ion implantation of impurities of the second conductivity type with the gate electrode serving as a mask so that the source, drain and channel regions are self-aligned to the gate electrode.
FET operating characteristics are determined by many different aspects of the FET structure including the thickness of the gate oxide layer. The upper limit on the operating voltage of the FET largely derives from the voltage at which the gate oxide layer undergoes dielectric breakdown, which in turn is largely determined by the thickness of the gate oxide layer. Because FETs used in different applications are designed to operate at different operating voltages, FETs in practical applications incorporate different thicknesses of gate oxide layers to accommodate the different operating voltages. FET's may also have different thicknesses of gate oxide to facilitate either high speed operation (thinner gate oxide) or low leakage (thicker gate oxide). Thus, FETs within memory devices might be formed having one thickness of gate oxide, while FETs in high speed, low voltage logic circuits might have a second, significantly thinner gate oxide layer. Most often, memory and logic circuits are segregated on separate chips. When memory and logic circuits are formed on separate chips, the desired gate oxide thicknesses are achieved by using different global thermal oxidation procedures during manufacture to grow the different thicknesses of gate oxides. Different thicknesses of gate oxide are readily provided by exposing the different substrates to oxidizing environments for different amounts of time.
Recently, an increasing number of chip designs have been proposed which would incorporate circuits on a single chip that use FETs having different thicknesses of gate oxides, whether to obtain different operating voltages or to vary other operating characteristics. For example, chip designs have been proposed which include logic circuits using FETs having thinner gate oxide layers and which include memory circuits using FETs having thicker gate oxide layers. To implement these designs successfully, it is necessary to form FETs having different gate oxide thicknesses on the same chip. This might be accomplished by masking portions of the chip and performing different thermal oxidation processes for each of the different portions of the chip. It will be appreciated that implementation of the multiple masking steps and multiple thermal oxidation steps is typically quite complicated. To maintain the integrity of a gate oxide layer, it is necessary to cover the gate oxide layer with the polysilicon layer that will be formed into the gate electrodes of the FETs in that region before any other processing steps are performed. Thus, if a chip design requires FETs having multiple distinct gate oxide thicknesses, it would be necessary to mask the chip in a manner which exposes only those portions of the chip where FETs incorporating a first thickness of gate oxide are to be formed. The exposed portions of the chip are then thermally oxidized and polysilicon is deposited over the chip. The polysilicon layer must then be removed over those other portions of the chip where other thicknesses of gate oxide are to be grown. This process is repeated for each of the different thicknesses of gate oxide to be formed on the chip.
This strategy of multiple masking steps and multiple thermal oxidation steps has disadvantages, however. Obviously, the process flow used in forming FETs with different thicknesses of gate oxide is much more complicated, time consuming and demanding of manufacturing resources than more conventional, uniform gate oxide FET manufacturing processes. Such processes expose portions of the substrate and the gate electrode polysilicon to multiple etching steps and multiple photoresist masks, which can introduce defects to later processing steps. This strategy requires multiple thermal oxidation steps which in turn requires that some of the gate oxide layers undergo multiple high temperature processing steps, which can reduce the reliability of the gate oxide layers and thereby reduce the reliability of the FETs incorporating the gate oxide layers.
It would accordingly be desirable to provide an improved method of forming different thicknesses of gate oxide layers on a single chip.